Mail Archives: geda-help/2014/04/06/00:34:49
Hello Carlos,
On Sat, 5 Apr 2014, Carlos Moreno wrote:
> Here's the screenshot (using R025 for the resistors' footprints,
> and after doing disperse all elements, optimize rat nets, and
> moving R2 --- just to see which line was what; the two rat
> lines where parallel, so it looked like just one line going from
> R3 to R1): http://www.mochima.com/tmp/pcb-screenshot.png
Judging from this one, it seems like the problem is specific to U1 - the
connection between the resistors worked well. However, I can't check again
because you have changed a few things since (resistor footprints, the
symbol behind LME, as you mentioned).
If you try again, please repost the files so we have a the screenshot for
the same files as the rest. I'd the the following extra steps:
1. hover the mouse over the middle of U1, between pins, and press 'd';
this would annotate each pin with its pin number. Even better please
do this for the resistors as well. Please make a screenshot with these
annotations.
2. upload the pcb tight after gsch2pcb, then open from
pcb, load netlist, disperse, optimize rats, make sure the same
resistor-only-net has the rats then save the pcb and upload that as well.
3. please upload the .net file gsch2pcb spits out
4. please post the error log for this session (again there's been a lot
changed, footpritns, symbols...)
The netlist is embedded in the .pcb, so if PCB does something bad to the
netlist internally, comparing the files produced in step 2. and 3. would
help. If PCB has problems with the pin numbering, the screenshot of 1.
woudl show. Currently these are the things I think could go wrong there.
>
> *However* --- there may have been something broken with the
> symbol back then (for example, yesterday, after your first
> message, I went back and checked; the LME49811.sym had
> the NC pins with pintype=nc --- I know, shame on me for being
> that sloppy!! :-) As you noticed, I fixed them, and they now
> have pintype=pas)
I think that doesn't matter in the gshcem -> PCB flow, but indeed, better
to fix it.
>
> Another possibility is that the procedure I'm following is not
> correct --- I may be missing some steps, or doing them in the
> wrong order, etc.
I'd be surprised - the latest screenshot shows half of the netlist is
fine. It should work even if you have a valid netlist and import a
footprint to your PCB later or replace one with a delete/import combo.
>
> I guess I'll try again with the exact files I have now (the ones
> that worked on your side) working with the newer versions
> installed from source, and if it still doesn't work, I'll write again
> and either send screenshots or I could go to the extreme of
> uploading a video of my screen while executing the workflow.
Good luck!
Regards,
Tibor
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